Features 

Hot-pluggable QSFP28 form factor and Compliant with QSFP+ MSA.

• I2C management interface

• RoHS-6 compliant (lead-free)

• Power dissipation < 3.5W

• 0°C to 70°C Commercial Temperature Range

• Single 3.3V power supply

• Maximum link length of 40km on SMF

• Optical 26.6GBaud PAM4

• IEEE STD 802.3cd Compliant

• 50GAUI-2 Serial Electrical Interface support

• Duplex LC connector

   

Applications                                    

• 50G ER applications

• Other Optical Links

Standards

• Compliant with QSFP+ MSA.

• Compliant with SFF-8636

• Compliant with IEEE802.3cd

• Compliant with IEEE802.3bm

• Compliant with RoHS6

Description

The HG Genuine MTRQ-1EA42 QSFP28 transceiver modules is a high performance, cost effective module for 50 Gigabit Ethernet links up to 40km over single mode fiber. They are compliant with the QSFP28 MSA, and IEEE 802.3cd. The Optical transmitter integrated with DSP that translated two lans 26.6GBd NRZ to 26.6GBd PAM4.It contains a single LC connector for the optical interface and a 38-pin connector for the electrical interface. Digital Diagnostics functions are available via a 2-wire serial interface, as specified SFF-8636.

Specifications

Table1-Absolute Maximum Ratings

Recommended working conditions

Table2-Recommended Operating Conditions

Optical，Electrical Characteristic

Tested under recommended operating conditions, unless otherwise noted

Table3-Transmitter Operating Characteristic-Optical

Notes:

[1] Min average power is informative and not the principal indicator of signal strength. Power below this value cannot be compliant; however, a value above this does not ensure compliance.

[2] Even if the TDECQ < 1 .4dB, the OMA_outer (min) must exceed this value.

[3] Transmitter reflectance is defined looking into the transmitter.

Table4- Receiver Operating Characteristic-Optical

Notes:

[1] The receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal having this average power level

[2] Average receive power (min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance.

[3] Receiver sensitivity (OMAouter) (max) is informative and is defined for a transmitter with a value of SECQ up to 3.2 dB for 50GBASE-ER. The value of BER is 2e-4(before FEC).

[4] Measured with conformance test signal at TP3 (see 139.7.10) for the BER specified in 139.1.1 (IEEE802.3cd)

[5] These test conditions are for measuring stressed receiver sensitivity. They are not characteristics of the receiver

Table5- Operating Characteristic- Electrical

Digital Diagnostic Functions and Control and Status I/O Timing Characteristics

Table6- Digital Diagnostic Functions

Table7- Control and Status I/O Timing Characteristics

Notes:

[1] Time from power on, hot plug or rising edge of reset until the module is fully functional. This time does not apply to non-Power level 0 modules in Low Power State.

[2] A Reset is generated by a low level longer than t_reset_init present on the ResetL input.

[3] Time from power on until the module responds to data transmission over the two wire serial bus.

[4] Time from assertion of LPMode (Vin:LPMode = Vih) until module power consumption reaches Power Level 1.

[5] Time from deassertion of LPMode (Vin:LPMode = Vil) until module is fully functional,

[6] Time from occurrence of condition triggering IntL until Vout:IntL=Vol.

[7] Time from clear on read operation of associated flag until Vout:IntL=Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.

[8] Time from Rx LOS state to Rx LOS bit set (value = 1b) and IntL asserted.

[9] Time from Tx Fault state to Tx Fault bit set (value = 1b) and IntL asserted.

[10] Time from condition triggering flag to associated flag bit set (value = 1b) and IntL asserted.

[11] Time from mask bit set (value = 1b) until associated IntL assertion is inhibited.

[12] Time from mask bit cleared (value = 0b) until associated IntL operation resumes.

[13] Time from change of state of Application or Rate Select bit until transmitter or receiver bandwidth is in conformance with appropriate specification.

[14] Time from P_Down bit set (value = 1b) until module power consumption reaches Power Level 1

[15] Time from P_Down bit cleared (value = 0b) until module is fully functional.

Pin-out Definition

Table8-Pin Function Definitions

Notes:

[1] GND is the symbol for signal and supply (power) common for the QSFP+ module. All are common within the QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane.

[2] Vcc Rx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 7. Vcc Rx Vcc1 and VccTx may be internally connected within the QSFP+ Module in any combination. The connector pins are each rated for a maximum current of 500 mA.

[3] NC is Not Connect.

Block Diagram of Transceiver

Recommended Interface Circuit

The host board should use the power supply filtering equivalent to that shown in Figure4. Any voltage drop across a filter network on the host is counted against the host DC set point accuracy specification. Inductors with DC resistance of less than 0.1 Ohm should be used in order to maintain the required voltage at the Host Edge Card Connector. It is recommended that the 22 uF capacitors each have an equivalent series resistance of 0.22 ohm.

Mechanical Dimensions

Unit is millimeter.

Digital Diagnostic Memory Map

Table9-EEPROM Serial ID Memory Contents (Upper page 00h)

 Table10-EEPROM DDM Alarm & Warning Threshold (Upper page 03h)

Ordering Information

Table11- Ordering Information

Contact Information

Wuhan Huagong Genuine Optics Technology Co., Ltd

Address: Science & Technology Region of HUST, Donghu High-Tech Zone

Wuhan, Hubei Province, 430223, China

• Tel: +86-27-87180102  

• Fax: +86-27-87180220   

  Email: market@dian-shibang.com

  Website: http://www.dian-shibang.com

   

  Statement

  HG Genuine possesses the authority for ultimate explanation of all information contained in this document, which is subject to change without prior notice. All the information was obtained in specific environments; and HG Genuine will not be responsible for verifying the products performance in customers’ operating environments, neither liable for the performance of users' products. All information contained is only for the users' reference and shall not be considered as warranted characteristics. HG Genuine will not be liable for damages arising directly or indirectly from any use of the information contained in this document.

  Publishing Date: 18 Feb,2019

   

  Copyright Ó HG Genuine

  All Right Reserved